The present invention relates in general to semiconductor packaging, and more specifically to a package for a micro-electromechanical device.
Micro-electromechanical devices (MEMS) make use of semiconductor technology to fabricate microscopic mechanisms on the surface of a semiconductor wafer. These devices have a wide range of uses, such as accelerometers, pressure sensors, actuators, and other types of sensors. Due to their size, the microscopic mechanisms are extremely vulnerable to damage from handling, to particles, to air flow and moisture; therefore, packaging of the devices presents many more challenges than conventional integrated circuits. Many of the devices have moving parts which requires a cavity surrounding the device to allow the device to move freely, and so for the most part, the devices have been packaged in ceramic or metal packages having a cavity. However, these options are both an expensive, poorly automated process and they do not resolve the issue of particles from the sawing process during separating the individual devices on a wafer. Further, they are not necessarily optimized for device reliability and performance.
In an attempt to circumvent the problem, such devices have been encapsulated at the wafer level, before separating into individual chips. This provides a technique for avoiding damage to unprotected mechanisms which occurs during the separation and packaging process. In very early work on wafer level packaging, the devices were covered with a thick layer of silicon dioxide during the final wafer processing step. This, of course, was completely unsatisfactory for devices having moving parts.
A more satisfactory solution was provided by V. J. Adams, et al in U.S. Pat. No. 5,323,051 which is incorporated herein by reference. This patent describes a wafer having active devices in a silicon wafer substrate with a second silicon wafer adhered to the substrate to form a cap, and a pattern of walls on the cap formed from frit glass which surround the individual devices. The walls are patterned to surround each device, allowing a hermetic package around each unit after the cap and substrate are bonded by firing the glass. Holes in the cap wafer are provided for electrical connection to the electrodes which pass through the frit glass wall seals. Following bonding of the two wafers, the devices are separated with minimal concern for debris from the sawing process, and each device is housed in a hermetic cavity. There are a number of advantages to this prior art approach, including matched thermal expansion coefficient between the silicon wafer substrate and cap silicon wafers, protection of the devices, and the potential for assembly of the individual devices into low cost plastic packages.
However, fabrication processes for the existing art are not compatible with assembly techniques or equipment which is in well known in state-of-the-art wafer fabrication and/or plastic assembly facilities. Instead, it makes use of screen printing a frit glass compound, which has previously been used in the fabrication of ceramic packages and substrates, but is atypical of current high volume semiconductor processing facilities. Further, a process which relies on a relatively thick patterned frit glass across the surface of a wafer is subject to non-uniformity in stand-off height, as well as to run out or bleed of the molten glass into active areas of the devices. Potential bleed of the glass film into the active circuitry requires that large perimeters be allowed to avoid such a problem, thereby decreasing the number of devices that can be assembled on a given substrate. The large perimeter area required to avoid run-out of the glass also necessitates that the conductor lengths between active circuit and contact pad be long, thereby increasing the lead inductance.
A need exists for a method of packaging micro-electromechanical devices fabricated on a semiconductor wafer before the wafer is diced into individual chips, by making use of state-of-the-art high volume manufacturing techniques from either wafer fabrication or from plastic package assembly. The method must provide a well controlled cavity within which micro-machined parts are free to move, have thermal characteristics which closely match that of the device, allow access for electrical contacts, and be optimized for device performance.
The present invention provides an improved wafer level encapsulated micro-electromechanical device and method of manufacture for devices fabricated on a semiconductor wafer. The active devices are encapsulated at the wafer level before dicing by adhering a cap wafer having cavities patterned by anisotropic etching of the cap. The cavities correspond to the location of the active circuits, and the unetched portions provide walls which are topped by a thin film of glass sputtered through a patterned mask. The cap wafer is adhered to the substrate by reflowing the glass film and forming a hermetic cavity around each active circuit. Openings for test probes and bond wires are provided through the cap wafer prior to aligning the two wafers and reflowing the glass. The assembled wafers are tested electrically in wafer form by probing with conventional test equipment. The tested devices are subsequently processed using conventional plastic molded package assembly techniques, including dicing with automated saws, attaching the devices to a lead frame, wire bonding through the openings in the cap, and encapsulating with plastic molding compounds.
Precision of the etched cavities and walls, coupled with thin film glass sealing of the wafers minimizes run-out or bleed of the glass into active areas, thereby allowing the circuit and contacts to be spaced in close proximity, supporting both higher density of circuits on the wafers, as well as short contact leads with lower resistivity.
An alternate method for adhering the substrate and recessed cap wafers makes use of solder reflow processing, rather than glass. Advantages include low temperature processing, potential for a ground ring surrounding the circuit, and compatibility with area array packages with solder contacts.
Both embodiments make use of manufacturing equipment and processes currently in production at state-of-the-art wafer fabrication and packaging assembly sites.